The present invention relates to a semiconductor device including a protecting circuit which is capable of preventing the semiconductor device from a rapid surge. The present invention is applicable to insulated gate transistors, such as power metal oxide semiconductor field effect transistors (abbreviated MOSFETs) and insulated gate bipolar transistors (abbreviated IGBTs).
FIG. 22 shows a conventional semiconductor device. A protecting apparatus of this conventional semiconductor device comprises a serial circuit 3 consisting of a plurality of clamping Zener diodes. The serial circuit 3 is connected between drain and gate electrodes of a double diffused metal oxide semiconductor (DMOS) field-effect transistor 2 which is actuated by a gate actuating circuit 8. The purpose of providing the serial circuit 3 is to improve the surge durability against a surge voltage caused by an inductive load 1.
According to the circuit arrangement shown in FIG. 22, when the semiconductor device receives a surge voltage applied from the inductive load 1, each Zener diode in the serial circuit 3 causes breakdown at a predetermined voltage level lower than that of the field-effect transistor 2. Thus, the field-effect transistor 2 turns on in response to electric charge input to the gate electrode thereof. Surge current, corresponding to the surge voltage, flows through the field-effect transistor 2. In the following description, the field-effect transistor is referred to or abbreviated as FET.
As the operation resistance of FET 2 has a positive temperature coefficient, no current concentration occurs. Accordingly, FET 2 causes no internal breakdown. A parasitic transistor 2a of FET 2 does not operate. The surge durability of the semiconductor device is improved.
In this semiconductor device, each Zener diode in the serial circuit 3 may be a multiple polysilicon Zener diode including alternately doped boron and phosphor, or a multiple Zener diode formed by diffusing base and emitter layers in a power integrated circuit.
Thus, the Zener diodes are not large in chip size. The overall size of the Zener diodes is generally small compared with that of FET 2.
The internal resistance of all Zener diodes in the serial circuit 3 is usually a large value equal to approximately 1 kxcexa9. To allow the current to smoothly flow, it is necessary to maintain breakdown voltage of each Zener diode (which is usually 10V lower than the withstand voltage of FET 2). Thus, a sufficiently large bias cannot be applied to the gate electrode of FET 2. Hence, a current amount flowing in response to the turning-on operation of FET 2 is small. In other words, it is difficult to sufficiently improve the durability against a rapid and large-current surge caused by an electrostatic discharge (abbreviated ESD, hereinafter).
FIG. 23 shows a conventional semiconductor device proposed in the Unexamined Japanese patent publication No. 8-64812.
According to the circuit arrangement shown in FIG. 23, a protecting circuit 4, a back-flow preventing Zener diode 5 and a resister 6 are connected between an inductive load 1 and the gate electrode of FET 2.
The protecting circuit 4 includes a DMOS-FET 4a. This FET 4a has a drain electrode connected to a drain electrode of FET 2 and a source electrode connected via the Zener diode 5 and the resister 6 to the gate electrode of FET 2.
Furthermore, the protecting circuit 4 includes a capacitor 4b which is connected between the gate and drain electrodes of FET 4a. The capacitor 4b is connected in parallel with a serial circuit which consists of a plurality of clamping Zener diodes 4c connected in series. A resister 7 is interposed between the gate and source electrodes of FET 4a. 
When a surge voltage caused by the inductive load 1 is applied to the protecting circuit 4, the surge current passes the capacitor 4a and flows into the gate electrode of FET 4a. Thus, FET 4a turns on in the initial stage.
In response to the turning-on operation of FET 4a, the surge current based on the surge voltage caused by the inductive load 1 flows into the gate electrode of FET 2 via FET 4a, Zener diode 5 and the resister 6, so as to turn on FET 2. Thus, the surge current flows across FET 2 from the inductive load 1.
However, when the surge voltage is an ESD surge causing rapid and large current (having operation time of approximately 10 nsec, peak current of approximately 160 A, 150xcexa9, 150 pF, and 25 kV discharge), it is necessary to quickly increase the gate potential of FET 2 to a higher level (e.g., 10 times the threshold value of FET 2) in a short time (e.g., within 1 nsec) by turning on FET 4a. When FET 2 turns on, the surge current flows across FET 2.
However, as described above, the resister 6 is interposed between the Zener diode 5 and the gate electrode of FET 2. The resister 6 limits the charge current flowing into the gate electrode of FET 2. Thus, it becomes impossible to quickly and sufficiently charge the gate electrode of FET 2.
Accordingly, there is the possibility that the internal diode of FET 2 induces avalanche breakdown. In a worst case, the parasitic bipolar transistor of FET 2 may operate and induce permanent damage due to current concentration. As a result, the ESD durability of FET 2 (or the semiconductor device) may deteriorate.
In view of the foregoing, an object of the present invention is to provide a protecting apparatus for a semiconductor device which is capable of surely protecting the semiconductor device from the rapid surge, such as ESD surge.
In order to accomplish this and other related objects, the present invention provides a protecting apparatus for protecting a main transistor formed on a semiconductor substrate from a rapid surge, comprising a back-flow preventing Zener diode having a cathode connected directly to a control terminal of the main transistor for preventing current from flowing in a predetermined direction, a protecting transistor having an output terminal connected to an anode of the back-flow preventing Zener diode and an input terminal connected to an input terminal of the main transistor, and a protecting capacitor connected between a control terminal of the protecting transistor and the input terminal of the main transistor for allowing initial surge current, when caused based on a rapid surge, to flow into the control terminal of the protecting transistor. The protecting transistor, when turning on in response to the initial surge current, allows next surge current succeeding the initial surge current to flow into the control terminal of the main transistor via the back-flow preventing Zener diode. And, the main transistor, when turning on in response to the next surge current, allows late surge current succeeding the next surge current to flow therethrough.
According to this arrangement, no resister is connected between the protecting transistor and the main transistor. Only the back-flow preventing Zener diode, having a small internal resistance value, is connected between the protecting transistor and the main transistor. Thus, the current amount of next surge current flowing through the protecting transistor is not limited or suppressed. The next surge current smoothly flows into the control terminal of the main transistor.
With this arrangement, the next surge current serving as charging current quickly and sufficiently flows into the control terminal of the main transistor. Hence, the main transistor turns on immediately without inducing the avalanche breakdown of the diode constituting a parasitic element or without activating the transistor constituting a parasitic element. The late surge current can smoothly flow through the main transistor. Thus, it becomes possible to improve the ESD durability of the semiconductor device.
The present invention provides another protecting apparatus for protecting a main transistor formed on a semiconductor substrate from a rapid surge. The protecting apparatus comprises a back-flow preventing Zener diode having a cathode connected directly to a control terminal of the main transistor for preventing current from flowing in a predetermined direction. A protecting transistor has an output terminal connected to an anode of the back-flow preventing Zener diode and an input terminal connected to an input terminal of the main transistor. A Zener diode circuit is connected between a control terminal of the protecting transistor and the input terminal of the main transistor for allowing initial surge current, when caused based on a rapid surge, to flow into the control terminal of the protecting transistor. The protecting transistor, when turning on in response to the initial surge current, allows next surge current succeeding the initial surge current to flow into the control terminal of the main transistor via the back-flow preventing Zener diode. And, the main transistor, when turning on in response to the next surge current, allows late surge current succeeding the next surge current to flow therethrough.
According to this arrangement, when the next surge current flows into the input terminal of the protecting transistor, the Zener diodes in the Zener diode circuit causes breakdown to allow the next surge current to flow into the control terminal of the protecting transistor. The protecting transistor turns on in response to the input next surge current. In response to the turning-on operation of the protecting transistor, the main transistor turns on so as to allow the late surge current to flow therethrough.
Furthermore, it is preferable that the main transistor and the protecting transistor are metal oxide semiconductor field-effect transistors. It is also preferable that an auxiliary protecting transistor is connected between the protecting transistor and the protecting capacitor or the Zener diode circuit for amplifying the initial surge current and supplying the amplified initial surge current to the control terminal of the protecting transistor.
According to this arrangement, the initial surge current flows through the protecting capacitor or the Zener diode circuit. The auxiliary protecting transistor is charged at its control terminal by the protecting capacitor or the Zener diode circuit. The protecting transistor is charged at its control terminal by the turned-on auxiliary protecting transistor. Therefore, the electric potential of the control terminal of the auxiliary protecting transistor can be increased to a higher voltage level. Thus, a large amount of current flows through the main transistor.
As a result, the bias voltage level of the control terminal of the main transistor becomes higher. The maximum value of the saturated current responsive to the turning-on operation of the main transistor becomes large. Accordingly, the ESD durability can be improved.
It is preferable that all of the main transistor, the protecting transistor, and the auxiliary protecting transistor are metal oxide semiconductor field-effect transistors.
Furthermore, it is preferable that the protecting transistor comprises a built-in (or internal) back-flow preventing Zener diode.
Furthermore, it is preferable that a protecting Zener diode is connected in parallel with the protecting capacitor. A first initial surge current flows through the protecting capacitor. And, a second initial surge current, succeeding the first initial surge current, flows through the protecting Zener diode.
Furthermore, it is preferable that the main transistor is a metal oxide semiconductor field-effect transistor and the protecting transistor is a bipolar transistor. It is also preferable that the main transistor is a metal oxide semiconductor field-effect transistor, and the protecting transistor and the auxiliary protecting transistor are bipolar transistors.
The present invention provides another protecting apparatus for protecting a main transistor formed on a semiconductor substrate from a rapid surge, comprising a back-flow preventing Zener diode having a cathode connected to a control terminal of the main transistor for preventing current from flowing in a predetermined direction, a protecting Zener diode having an anode connected to an anode of the back-flow preventing Zener diode and a cathode connected to an input terminal of the main transistor, and a protecting capacitor connected in parallel with the protecting Zener diode for allowing initial surge current, when caused based on a rapid surge, to flow into the control terminal of the main transistor via the back-flow preventing Zener diode. The protecting Zener diode allows next surge current succeeding the initial surge current to flow into the control terminal of the main transistor via the back-flow preventing Zener diode, and the main transistor, when turning on in response to the initial surge current or the next surge current, allows late surge current succeeding the next surge current to flow therethrough.
According to this arrangement, the initial surge current flows into the control terminal of the main transistor via the protecting capacitor and the back-flow flow preventing Zener diode. Then, the next surge current flows into the control terminal of the main transistor via the protecting Zener diode, and the back-flow preventing Zener diode.
No resister is connected between the anode of the protecting Zener diode and the control terminal of the main transistor. Only the back-flow preventing Zener diode, having a small internal resistance value, is connected between the anode of the protecting Zener diode and the control terminal of the main transistor.
Thus, the current amounts of initial surge current and next surge current flowing through the back-flow preventing Zener diode are not limited or suppressed. Both the initial surge current and the next surge current successively flow quickly and sufficiently into the control terminal of the main transistor as charge current.
Hence, the main transistor turns on immediately without inducing the avalanche breakdown of the diode constituting a parasitic element or without activating the transistor constituting a parasitic element. The late surge current can smoothly flow through the main transistor. Thus, it becomes possible to improve the ESD durability of the semiconductor device.
The present invention provides another protecting apparatus for protecting a main transistor formed on a semiconductor substrate from a rapid surge, comprising a back-flow preventing Zener diode having a cathode connected to a control terminal of the main transistor for preventing current from flowing in a predetermined direction, and a protecting transistor circuit including a plurality of transistors consisting of an initial transistor and at least one succeeding transistor connected in a Darlington connecting pattern, each transistor having an output terminal connected to an anode of the back-flow preventing Zener diode and an input terminal connected to an input terminal of the main transistor. The protecting transistor circuit turns on the succeeding transistor in response to initial surge current caused based on a rapid surge, and further turns on the initial transistor in response to the turning of the succeeding transistor. The initial transistor, when turning on, allows next surge current succeeding the initial surge current to flow into the control terminal of the main transistor. And, the main transistor, when turning on in response to the next surge current, allows late surge current succeeding the next surge current to flow therethrough.
According to this arrangement, the plurality of transistors connected in the Darlington connecting pattern sufficiently amplify the current flowing into the control terminal of the main transistor via the back-flow preventing Zener diode.
Hence, the main transistor turns on immediately. The late surge current can sufficiently flow through the main transistor without activating the parasitic element. As a result, it becomes possible to improve the ESD durability of the semiconductor device. In this case, it is preferable that the main transistor and each transistor in the protecting transistor circuit are metal oxide semiconductor field-effect transistors.
Furthermore, it is preferable that there is a protecting Zener diode connected in parallel with the protecting transistor. The protecting Zener diode has a cathode connected to the input terminal of the main transistor and an anode connected to the anode of the back-flow preventing Zener diode.
The main transistor controls current supplied to an inductive load connected to the input terminal of the main transistor. The inductive load generates an inductive load surge when the current supply is stopped. The rapid surge is caused by an electrostatic discharge. The inductive load surge is small in frequency than the rapid surge. And, the protecting Zener diode causes breakdown in response to the inductive load surge so as to turn on the main transistor prior to a turning-on operation of the protecting transistor by the protecting capacitor.
Accordingly, the inductive load surge having a smaller frequency compared with the rapid surge causes the breakdown and turns on the main transistor. Hence, it becomes possible to protect the main transistor against the inductive load surge as well as the rapid surge. In this case, it is preferable that the rapid surge has a frequency in the range of GHz, and the inductive load surge has a frequency in the range of kHz. A relationship Rd greater than Rh is satisfied, where Rh represents an operation resistance in a flowing path of the next surge current flowing into the control terminal of the main transistor via the back-flow preventing Zener diode, and Rd represents an actuating resistance disposed in a path connected to an actuating circuit for actuating the main transistor.
With this arrangement, it becomes possible to increase the voltage drop at the actuating resistance to a higher voltage level sufficiently higher than the threshold voltage of the main transistor. This voltage drop is required for operating the main transistor when the ESD surge is applied.
Furthermore, it is preferable that the main transistor is formed as a cell region including a plurality of single cells on the semiconductor substrate. The control terminal of the main transistor is formed as a common electrode of the plurality of single cells. The control terminal of the main transistor extends out of the cell region. A signal applying electrode, connected to the control terminal of the main transistor, is formed on a surface of the semiconductor substrate so as to surround the cell region. The signal applying electrode is connected to the cathode of the back-flow preventing Zener diode. A wiring width of the signal applying electrode is wider than a wiring width of a lead connecting the cathode of the back-flow preventing Zener diode to the signal applying electrode.
Moreover, another object of the present invention is to provide a semiconductor device which is capable of improving the surge durability by raising the gate potential of the transistor so as to increase the operation current of the transistor.
In order to accomplish this and other related objects, the present invention provides a semiconductor device comprising an insulated gate transistor disposed in a current path of an electric load, a gate voltage boosting element having one end connected to a gate electrode of the insulated gate transistor so as to operate in response to a surge applied from a high-voltage terminal of the insulated gate transistor, a wiring member serving as a parasitic inductance against the applied surge. The wiring member is connected in parallel with the gate voltage boosting element with respect to the high-voltage terminal of the insulated gate transistor. The insulated gate transistor and the gate voltage boosting element are formed in a chip, while the wiring member is provided outside the chip.
According to this circuit arrangement, the wiring member (e.g., bonding wire, conductive pattern on a printed circuit board) is utilized as a parasitic inductance (i.e., impedance). This parasitic inductance boosts the input voltage of the gate voltage boosting element (e.g., Zener diode). Thus, it becomes possible to raise the gate potential of the insulated gate transistor. A great amount of operation current flows through the insulated gate transistor, thereby improving the surge durability.